In the evolutionary development of digital integrated circuit ("IC") chips, their capabilities have improved dramatically. These improvements include a sharp increase in the speed at which these IC chips process data. Coupled with these improvements is a decrease in the package size of these chips.
One of the problems that has affected the operation of advanced digital IC chips is simultaneous switching noise. This noise is generated by a chip's output pins switching from a driving current to a sinking current or vice-versa in a very short period of time, for instance in 1-3 ns (nanoseconds). Thus, the greater the number of output pins that simultaneously switch in this short period of time, the greater the noise level. When this simultaneous switching noise becomes great enough, it may cause data transmission errors.
Simultaneous switching noise was not a critical problem in older digital IC chip designs because the cycle times were much longer and the switching rise and fall times were slower than those for the advanced digital IC chips. Since the cycle times in these older chip designs were much longer than those in the advanced digital IC chips, output pin switching could be spread out over this long cycle time which greatly reduced the likelihood that simultaneous switching noise would be great enough to cause data transmission errors.
These longer cycle times also lended themselves to other schemes for reducing the chances of generating enough simultaneous switching noise to cause data transmission errors. For example, longer cycle times could be divided into portions that were devoted to just data transmission and others devoted to just switching the output pins. The portions devoted to switching the output pins would be long enough to spread the switching out so that there was only a very small possibility that the simultaneous switching noise would ever reach a level sufficient to cause data transmission errors.
The luxury of long cycle times is not available in advanced digital IC chips. The few nanoseconds during which a requisite number of simultaneously switching output pins may generate a noise level that is sufficient to cause data transmission errors may be 1/2 or more of the cycle time of these advanced chips. Accordingly, there is not a sufficient cycle time to solve the simultaneous switching problem as it was done in older IC chip designs.
Simultaneous switching noise is proportional to the number of output pins that change during a particular short time period. There are situations in which changing from one output pattern to another will necessarily cause the simultaneous switching noise to be at a level high enough to cause data transmission errors. Therefore, there is some pattern dependency for generating data transmission errors. This can only be prevented by reducing the simultaneous switching noises.
There have been a number of suggested solutions to the simultaneous switching noise problem in advanced digital IC chips; however, these solutions either require that the digital IC chip undergo costly reconfiguration, or significantly affect the effective data bandwidth or the speed at which the digital IC chips process information.
One suggestion to reconfigure the digital IC chips is to make all of the output pins differential pins. Hence, each bit is transmitted by two complementary pins so that the net signaling current for that bit is zero. Even though the simultaneous switching noise is reduced and the full transition speeds are allowed, this scheme uses two output pins per bit which cuts the effective data bandwidth in half. Obviously, it will take twice as much time or twice as many output pins to get signals off a chip as it would for a chip configured with single-ended output pins. This solution is not desirable.
Another suggestion is to reconfigure the digital IC chips to include a greater number of ground pins or ensure that the chip has a ground level plane. These have the effect of reducing the inductance at single-ended output pins, and thereby the switching noise. Even when either one of these is provided and the inductance is reduced, there still is a substantial amount of inductance remaining at each output pin. Thus, it simply takes a larger number of simultaneously switching output pins to generate sufficient noise to cause data transmission errors.
Since most systems today are synchronous switching type systems, another suggestion is to wait to sample the output waveform after a time period that ensures that the simultaneous switching noise has died out. Obviously, this necessarily requires lengthening the cycle time which, as stated, is highly undesirable in fast switching parallel system such as advanced digital IC chips.
Another suggested method is simply to spread out the switching time but not to the extent that it was done in older digital IC chip designs. Again, this will require lengthening of the cycle time which is not desired.
In the past, an error detection method was used for long distance transmissions of serial data. According to this method, it is desirable to eliminate the DC component of the transmission. This is done by ensuring that an equal number "1s" and "0s" are transmitted in the serial data over a long period of time--an averaging method. This, however, would not be too effective with fast parallel switching networks of digital IC chips.
There is a need to overcome these problems and provide a system and method for reducing simultaneous switching noise, while at the same time providing effective error detection, all without significantly changing the effective data bandwidth.